 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| (R) ISL62882, ISL62882B Data Sheet April 1, 2009 FN6890.0 Multiphase PWM Regulator for IMVP-6.5TM Mobile CPUs The ISL62882 is a multiphase PWM buck regulator for miroprocessor core power supply. The multiphase buck converter uses interleaved phase to reduce the total output voltage ripple with each phase carrying a portion of the total load current, providing better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implementation area. The ISL62882 uses two integrated gate drivers to provide a complete solution. The PWM modulator is based on Intersil's Robust Ripple Regulator (R3) technologyTM. Compared with traditional modulators, the R3TM modulator commands variable switching frequency during load transients, achieving faster transient response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. The ISL62882 is fully compliant with IMVP-6.5TM specifications. It responds to PSI# and DPRSLPVR signals by adding or dropping Phase 2, adjusting overcurrent protection threshold accordingly, and entering/exiting diode emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete resistor or inductor DCR whose variation over temperature can be thermally compensated by a single NTC thermistor. It uses differential remote voltage sensing to accurately regulate the processor die voltage. The unique split LGATE function further increases light load efficiency. The adaptive body diode conduction time reduction function minimizes the body diode conduction loss in diode emulation mode. User-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. The ISL62882 offers the FB2 function to optimize 1-phase performance. The ISL62882B has the same functions as the ISL62882, but comes in a different package. Features * Precision Multiphase Core Voltage Regulation - 0.5% System Accuracy Over-Temperature - Enhanced Load Line Accuracy * Microprocessor Voltage Identification Input - 7-Bit VID Input, 0.300V to 1.500V in 12.5mV Steps - Supports VID Changes On-The-Fly * Supports Multiple Current Sensing Methods - Lossless Inductor DCR Current Sensing - Precision Resistor Current Sensing * Supports PSI# and DPRSLPVR modes * Superior Noise Immunity and Transient Response * Current Monitor and Thermal Monitor * Differential Remote Voltage Sensing * High Efficiency Across Entire Load Range * Programmable 1- or 2-Phase Operation * Two Integrated Gate Drivers * Excellent Dynamic Current Balance Between Phases * Split LGATE1 Drivers Increases Light Load Efficiency * FB2 Function Optimizes 1-Phase Mode Performance * Adaptive Body Diode Conduction Time Reduction * User-selectable Overshoot Reduction Function * Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Packages * Pb-Free (RoHS Compliant)) Applications * Notebook Computers 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL62882, ISL62882B . Ordering Information PART NUMBER (Note) ISL62882HRTZ ISL62882IRTZ ISL62882HRTZ-T* ISL62882IRTZ-T* ISL62882BHRTZ ISL62882BHRTZ-T* PART MARKING ISL62882 HRTZ ISL62882 IRTZ ISL62882 HRTZ ISL62882 IRTZ ISL62882 BHRTZ ISL62882 BHRTZ TEMP. RANGE (C) -10 to +100 -40 to +100 -10 to +100 -40 to +100 -10 to +100 -10 to +100 PACKAGE (Pb-Free) 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN Tape and Reel 40 Ld 5x5 TQFN Tape and Reel 48 Ld 6x6 TQFN 48 Ld 6x6 TQFN Tape and Reel PKG. DWG. L40.5x5 L40.5x5 L40.5x5 L40.5x5 L48.6x6 L48.6x6 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL62882 (40 LD TQFN) TOP VIEW DPRSLPVR ISL62882B (48 LD TQFN) TOP VIEW CLK_EN# DPRSLPVR VR_ON CLK_EN# VR_ON VID2 VID3 VID4 VID1 VID0 VID6 VID5 VID4 VID3 VID2 VID1 VID6 VID0 VID5 40 39 38 37 36 35 34 33 32 31 PGOOD 1 PSI# 2 RBIAS 3 VR_TT# 4 NTC 5 VW 6 GND PAD (BOTTOM) 30 BOOT2 29 UGATE2 28 PHASE2 27 VSSP2 26 LGATE2 25 VCCP 24 LGATE1b 23 LGATE1a 22 VSSP1 21 PHASE1 11 12 13 14 15 16 17 18 19 20 ISUM+ UGATE1 BOOT1 VDD ISEN1 VSEN IMON RTN VIN ISUMNC 1 PGOOD 2 PSI# 3 RBIAS 4 VR_TT# 5 NTC 6 GND 7 VW 8 COMP 9 FB 10 FB2 11 NC 12 48 47 46 45 44 43 42 41 40 39 38 37 36 BOOT2 35 UGATE2 34 PHASE2 33 VSSP2 32 LGATE2 (BOTTOM) 31 NC 30 VCCP 29 LGATE1b 28 LGATE1a 27 VSSP1 26 PHASE1 25 UGATE1 13 14 15 16 17 18 19 20 21 22 23 24 ISUM+ VSEN IMON RTN NC ISEN2 ISEN1 VDD NC BOOT1 FN6890.0 April 1, 2009 COMP 7 FB FB2 8 9 ISEN2 10 NC ISUM- 2 VIN NC ISL62882, ISL62882B Pin Function Description GND Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. VDD 5V bias power. VIN Battery supply voltage, used for feed-forward. PGOOD Power-Good open-drain output indicating when the regulator is able to supply regulated voltage. Pull up externally with a 680 resistor to VCCP or 1.9k to 3.3V. IMON An analog output. IMON outputs a current proportional to the regulator output current. BOOT1 Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot diode. PSI# Low load current indicator input. When asserted low, indicates a reduced load-current condition. RBIAS 147k Resistor to GND sets internal current reference. VR_TT# Thermal overload output indicator. UGATE1 Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the Phase-1 high-side MOSFET. NTC Thermistor input to VR_TT# circuit. PHASE1 Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase-1. VW A resistor from this pin to COMP programs the switching frequency (8k gives approximately 300kHz). COMP This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the overcurrent threshold. VSSP1 Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1 low-side MOSFETs. FB This pin is the inverting input of the error amplifier. FB2 There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve optimum performance. LGATE1a Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a pin to the gate of the Phase-1 low-side MOSFET that is active all the time. ISEN2 Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2. LGATE1b Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1 low-side MOSFET that is idle in deeper sleep mode. ISEN1 Individual current sensing for phase 1. VSEN Remote core voltage sense input. Connect to microprocessor die. VCCP Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1F of an MLCC capacitor to VSSP1 and VSSP2 pins respectively. RTN Remote voltage sensing return. Connect to ground at microprocessor die. LGATE2 Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the Phase-2 low-side MOSFET. ISUM- and ISUM+ Droop current sense input. 3 FN6890.0 April 1, 2009 ISL62882, ISL62882B VSSP2 Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2 pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET. VID0, VID1, VID2, VID3, VID4, VID5, VID6 VID input with VID0 = LSB and VID6 = MSB. VR_ON Voltage regulator enable input. A high level logic signal on this pin enables the regulator. PHASE2 Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase-2. DPRSLPVR Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor is in deeper sleep mode. CLK_EN# Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is within 10% of Vboot. UGATE2 Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the Phase-2 high-side MOSFET. NC No connect. BOOT2 Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot diode. BOTTOM (on ISL62882B) The bottom pad of ISL62882B is electrically connected to the GND pin inside the IC. 4 FN6890.0 April 1, 2009 ISL62882, ISL62882B Block Diagram VIN VSEN ISEN1 ISEN2 PGOOD CLK_EN# VDD VR_ON PSI# DPRSLPVR IBAL RBIAS PROTECTION VID0 VID1 VIN VID2 VID3 VID4 VID5 VID6 DAC & SOFT START MODULATOR CLOCK VDAC COMP VW COMP IBAL WOC OC VIN VDAC FLT MODE CONTROL PGOOD & CLK_EN# LOGIC 6A 54A 1.20V 1.24V VR_TT# CURRENT BALANCE NTC BOOT2 DRIVER PWM CONTROL LOGIC UGATE2 PHASE2 SHOOT THROUGH PROTECTION DRIVER LGATE2 VSSP2 BOOT1 E/A PWM CONTROL LOGIC RTN FB COMP VW DRIVER UGATE1 PHASE1 IBAL VIN VDAC SHOOT THROUGH PROTECTION VCCP DRIVER LGATE1A VSSP1 MODULATOR IDROOP FB2 IMON IMON ISUM+ ISUM2.5X CURRENT SENSE WOC CURRENT COMPARATORS OC NUMBER OF PHASES COMP 60A DRIVER LGATE1B GAIN SELECT ADJ. OCP THRESHOLD COMP GND 5 FN6890.0 April 1, 2009 ISL62882, ISL62882B Absolute Maximum Ratings Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10J) to BOOT LGATE1a and 1b and LGATE2 Voltage . . . -0.3V (DC) to VDD+0.3V LGATE1a and 1b . -2.5V (<20ns Pulse Width, 2.5J) to VDD+0.3V LGATE1a and 1b . . . -2.5V (<20ns Pulse Width, 5J) to VDD+0.3V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# . . . -0.3 to +7V Thermal Information Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 40 Ld TQFN Package . . . . . . . . . . . . . 32 3 48 Ld TQFN Package . . . . . . . . . . . . . 29 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V 5% Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V Ambient Temperature HRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100C IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100C Junction Temperature HRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +125C IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Limits established by characterization and are not production tested. Electrical Specifications Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PARAMETER INPUT POWER SUPPLY +5V Supply Current IVDD IVIN RVIN PORr PORf VR_ON = 3.3V VR_ON = 0V 4 4.6 1 1 mA A A k Battery Supply Current VIN Input Resistance Power-On-Reset Threshold VR_ON = 0V VR_ON = 3.3V VDD rising VDD falling No load; closed loop, active mode range VID = 0.75V - 1.50V, VID = 0.5V - 0.7375V VID = 0.3 - 0.4875V 4.00 900 4.35 4.15 4.5 V V SYSTEM AND REFERENCES System Accuracy HRTZ %Error (VCC_CORE) -0.5 -8 -15 -0.8 -10 -18 +0.5 +8 +15 +0.8 +10 +18 % mV mV % mV mV V V V 1.49 V IRTZ %Error (VCC_CORE) No load; closed loop, active mode range VID = 0.75V - 1.50V, VID = 0.5V - 0.7375V VID = 0.3 - 0.4875V VBOOT Maximum Output Voltage Minimum Output Voltage RBIAS Voltage CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range fSW(nom) Rfset = 7k, 3-channel operation, VCOMP = 1V VCC_CORE(max) VID = [0000000] VCC_CORE(min) VID = [1100000] RBIAS = 147k 1.0945 1.100 1.1055 1.500 0.300 1.45 1.47 285 200 300 315 500 kHz kHz 6 FN6890.0 April 1, 2009 ISL62882, ISL62882B Electrical Specifications Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PARAMETER AMPLIFIERS Current-Sense Amplifier Input Offset Error Amp DC Gain (Note 3) Error Amp Gain-Bandwidth Product (Note 3) ISEN Imbalance Voltage Input Bias Current POWER-GOOD AND PROTECTION MONITORS PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay GATE DRIVER UGATE Pull-Up Resistance (Note 3) UGATE Source Current (Note 3) UGATE Sink Resistance (Note 3) UGATE Sink Current (Note 3) LGATE1a&b Pull-Up Resistance (Note 3) LGATE1a&b Source Current (Note 3) LGATE1a&b Sink Resistance (Note 3) LGATE1a&b Sink Current (Note 3) UGATE1 to LGATE1a and 1b Deadtime LGATE1a and 1b to UGATE1 Deadtime LGATE2 Pull-Up Resistance (Note 3) LGATE2 Source Current (Note 3) LGATE2 Sink Resistance (Note 3) LGATE2 Sink Current (Note 3) UGATE2 to LGATE2 Deadtime LGATE2 to UGATE2 Deadtime BOOTSTRAP DIODE Forward Voltage Reverse Leakage PROTECTION Overvoltage Threshold Severe Overvoltage Threshold OC Threshold Offset at Rcomp = Open Circuit IFB = 0A Av0 GBW CL = 20pF Maximum of ISENs - Minimum of ISENs -0.15 90 18 +0.15 mV dB MHz 1 20 mV nA VOL IOH tpgd IPGOOD = 4mA PGOOD = 3.3V CLK_ENABLE# LOW to PGOOD HIGH -1 6.3 0.26 0.4 1 V A ms A A A A ns ns 7.6 8.9 RUGPU IUGSRC RUGPD IUGSNK RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR VF IR OVH OVHS 200mA Source Current UGATE - PHASE = 2.5V 250mA Sink Current UGATE - PHASE = 2.5V 250mA Source Current LGATE1a and 1b - VSSP1 = 2.5V 250mA Sink Current LGATE1a and 1b - VSSP1 = 2.5V UGATE1 falling to LGATE1a and 1b rising, no load LGATE1a and 1b falling to UGATE1 rising, no load 250mA Source Current LGATE2 - VSSP2 = 2.5V 250mA Sink Current LGATE2 - VSSP2 = 2.5V UGATE2 falling to LGATE2 rising, no load LGATE2 falling to UGATE2 rising, no load 1.0 2.0 1.0 2.0 2.0 1.0 1 2.0 23 28 1.0 2.0 0.5 4.0 23 28 1.5 1.5 3 1.8 1.5 A A ns ns 0.9 PVCC = 5V, IF = 2mA VR = 25V VSEN rising above setpoint for >1ms VSEN rising for >2s 2-phase configuration, ISUM- pin current 1-phase configuration, ISUM- pin current 150 1.525 18.3 8.2 0.58 0.2 V A 195 1.55 20.2 10.1 9 240 1.575 22.1 12.0 mV V A A mV Current Imbalance Threshold Undervoltage Threshold LOGIC THRESHOLDS VR_ON Input Low VR_ON Input High VIL(1.0V) HRTZ VIH(1.0V) IRTZ VIH(1.0V) UVf One ISEN above another ISEN for >1.2ms VSEN falling below setpoint for >1.2ms -355 -295 -235 mV 0.3 0.7 0.75 V V V 7 FN6890.0 April 1, 2009 ISL62882, ISL62882B Electrical Specifications Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL VIL(1.0V) VIH(1.0V) NTC = 1.3V V (NTC) falling RTT VOL IOH IIMON I = 20mA 0.7 TEST CONDITIONS MIN TYP MAX 0.3 UNITS V V PARAMETER VID0-VID6, PSI#, and DPRSLPVR Input Low VID0-VID6, PSI#, and DPRSLPVR Input High THERMAL MONITOR NTC Source Current Over-Temperature Threshold VR_TT# Low Output Resistance CLK_EN# OUTPUT LEVELS CLK_EN# Low Output Voltage CLK_EN# Leakage Current CURRENT MONITOR IMON Output Current 53 1.18 60 1.2 6.5 67 1.22 9 A V I = 4mA CLK_EN# = 3.3V -1 0.26 0.4 1 V A ISUM- pin current = 20A ISUM- pin current = 10A ISUM- pin current = 5A 108 51 22 120 60 30 1.1 275 132 69 37.5 1.15 A A A V A IMON Clamp Voltage Current Sinking Capability INPUTS VR_ON Leakage Current VIMONCLAMP IVR_ON IVIDx IPSI# IDPRSLPVR VR_ON = 0V VR_ON = 1V -1 0 0 1 A A A 1 A A 1 A A 1 A VIDx Leakage Current VIDx = 0V VIDx = 1V -1 0 0.45 PSI# Leakage Current PSI# = 0V PSI# = 1V -1 0 0.45 DPRSLPVR Leakage Current DPRSLPVR = 0V DPRSLPVR = 1V -1 0 0.45 SLEW RATE Slew Rate (For VID Change) SR 5 6.5 mV/s Gate Driver Timing Diagram PWM tLGFUGR tRU UGATE 1V tFU LGATE 1V tRL tUGFLGR tFL 8 FN6890.0 April 1, 2009 ISL62882, ISL62882B Simplified Application Circuits V+5 Rbias Rntc o V+5 Vin VIN VDD VCCP RBIAS C NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 Cs2 ISEN2 BOOT1 Rs2 Vin L2 Vo PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON ISL62882 UGATE1 COMP L1 Rdroop FB2 FB VSEN PHASE1 LGATE1b LGATE1a VSSP1 ISEN1 Cs1 ISUM+ Rs1 Rsum2 VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRis RTN Cis Ri Cn o Rn C Rsum1 FIGURE 1. TYPICAL APPLICATION CIRCUIT USING DCR SENSING V+5 Rbias Rntc o V+5 Vin VIN VDD VCCP RBIAS C NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 Cs2 ISEN2 BOOT1 Rs2 Vin L2 Rsen2 Vo IMVP6_PWRGD VR_TT# CLK_ENABLE# VID<0:6> PSI# DPRSLPVR VR_ON ISL62882 UGATE1 COMP L1 Rdroop FB2 FB VSEN PHASE1 LGATE1b LGATE1a VSSP1 ISEN1 Cs1 ISUM+ Rsen1 Rs1 Rsum2 VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRis RTN Cis Ri Cn Rsum1 FIGURE 2. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING 9 FN6890.0 April 1, 2009 ISL62882, ISL62882B Theory of Operation Multiphase R3TM Modulator VW Master Clock Master Clock Circuit Master COMP Clock Phase Vcrm Sequencer Crm Slave Circuit 1 VW Clock1 PWM1 Phase1 S Q R L1 Vo Co COMP VW Clock1 Clock2 Vcrm gmVo Master Clock Clock1 PWM1 Clock2 PWM2 VW IL1 Vcrs1 Crs1 gm Slave Circuit 2 VW Clock2 PWM2 Phase2 S Q R L2 IL2 Vcrs2 Crs2 gm Vcrs1 Vcrs2 FIGURE 5. R3TM MODULATOROPERATION PRINCIPLES IN LOAD INSERTION RESPONSE FIGURE 3. R3TM MODULATOR CIRCUIT VW Vcrm COMP Master Clock Clock1 PWM1 Clock2 PWM2 VW Hysteretic Window The ISL62882 is a multiphase regulators implementing Intel(R) IMVP-6.5TM protocol. It can be programmed for oneor two-phase operation for microprocessor core applications. It uses Intersil patented R3TM (Robust Ripple RegulatorTM) modulator. The R3TM modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 3 conceptually shows the ISL62882 multiphase R3TM modulator circuit, and Figure 4 shows the operation principles. A current source flows from the VW pin to the COMP pin, creating a voltage window set by the resistor between between the two pins. This voltage window is called VW window in the following discussion. Inside the IC, the modulator uses the master clock circuit to generate the clocks for the slave circuits. The modulator discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. Crm voltage Vcrm is a sawtooth waveform traversing between the VW and COMP voltages. It resets to VW when it hits COMP, and generates a one-shot master clock signal. A phase sequencer distributes the master clock signal to the slave circuits. If the ISL62882 is in 2-phase mode, the master clock signal will be distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of-phase. If the ISL62882 is in 1-phase mode, the master clock signal will be distributed to phases 1 only and be the clock1 signal. Each slave circuit has its own ripple capacitor Crs, whose voltage mimics the inductor ripple current. A gm amplifier converts the inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the clock signal, and the current source Vcrs2 Vcrs1 FIGURE 4. R3TM MODULATOROPERATION PRINCIPLES IN STEADY STATE 10 FN6890.0 April 1, 2009 ISL62882, ISL62882B charges Crs. When Crs voltage VCrs hits VW, the slave circuit turns off the PWM pulse, and the current source discharges Crs. Since the ISL62882 works with Vcrs, which are largeamplitude and noise-free synthesized signals, the ISL62882 achieves lower phase jitter than conventional hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode converters, the ISL62882 has an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. Figure 5 shows the operation principles during load insertion response. The COMP voltage rises during load insertion, generating the master clock signal more quickly, so the PWM pulses turn on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency PWM controllers. The VW voltage rises as the COMP voltage rises, making the PWM pulses wider. During load release response, the COMP voltage falls. It takes the master clock circuit longer to generate the next master clock signal so the PWM pulse is held off until needed. The VW voltage falls as the VW voltage falls, reducing the current PWM pulse width. This kind of behavior gives the ISL62882 excellent response speed. The fact that both phases share the same VW window voltage also ensures excellent dynamic current balance between phases. If the load current is light enough, as Figure 6 shows, the inductor current will reach and stay at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (DCM). If the load current is heavy enough, the inductor current will never reach 0A, and the regulator is in CCM although the controller is in DE mode. Figure 7 shows the operation principle in diode emulation mode at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size, therefore is the same, making the inductor current triangle the same in the three cases. The ISL62882 clamps the ripple capacitor voltage Vcrs in DE mode to make it mimic the inductor current. It takes the COMP voltage longer to hit Vcrs, naturally stretching the switching period. The inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. The reduced switching frequency helps increase light load efficiency. CCM/DCM Boundary VW Vcrs iL Vcrs VW Light DCM Diode Emulation and Period Stretching P hase UGATE LG ATE iL Vcrs VW Deep DCM iL IL FIGURE 7. PERIOD STRETCHING FIGURE 6. DIODE EMULATION Start-up Timing With the controller's VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic high threshold. The ISL62882 uses digital soft-start to ramp-up DAC to the boot voltage of 1.1V at about 2.5mV/s. Once the output voltage is within 10% of the boot voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low and DAC slews at 5mV/s to the voltage set by the VID pins. PGOOD is asserted high in approximately 7ms. Figure 8 shows the typical start-up timing. Similar results occur if VR_ON is tied to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold. ISL62882 can operate in diode emulation (DE) mode to improve light load efficiency. In DE mode, the low-side MOSFET conducts when the current is flowing from source to drain and doesn't not allow reverse current, emulating a diode. As Figure 6 shows, when LGATE is on, the low-side MOSFET carries current, creating negative voltage on the phase node due to the voltage drop across the ON-resistance. The ISL62882 monitors the current through monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. 11 FN6890.0 April 1, 2009 ISL62882, ISL62882B TABLE 1. VID TABLE (Continued) VDD VR_ON 2.5mV/s 800s DAC 13 Switching Cycles ~7ms FIGURE 8. SOFT-START WAVEFORMS VID6 VID5 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VO (V) 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 5mV/s 90% Vboot VID Command Voltage 0 0 0 0 0 0 0 0 0 CLK_EN# PGOOD Voltage Regulation and Load Line Implementation After the start sequence, the ISL62882 regulates the output voltage to the value set by the VID inputs per Table 1. The ISL62882 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75V to 1.5V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. TABLE 1. VID TABLE VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 12 FN6890.0 April 1, 2009 ISL62882, ISL62882B TABLE 1. VID TABLE (Continued) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VO (V) 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TABLE 1. VID TABLE (Continued) VID4 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 Rdroop FB Vdroop VCCSENSE VR Local Vo "Catch" Resistor VIDs RTN Idroop COMP E/A VDAC DAC VID<0:6> VSSSENSE Internal to IC X1 VSS "Catch" Resistor FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE IMPLEMENTATION As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to the load current to achieve the load line. The ISL62882 can sense the inductor current through the intrinsic DC Resistance (DCR) resistance of the inductors as shown in Figure 1 or through resistors in series with the inductors as shown in Figure 2. In both methods, capacitor Cn voltage represents the inductor total currents. A droop amplifier converts Cn voltage into an internal current source 13 FN6890.0 April 1, 2009 ISL62882, ISL62882B with the gain set by resistor Ri. The current source is used for load line implementation, current monitor and overcurrent protection. Figure 9 shows the load line implementation. The ISL62882 drives a current source Idroop out of the FB pin, described by Equation 1. 2xV Cn I droop = ----------------Ri (EQ. 1) Phase Current Balancing L2 PHASE2 ISEN2 CS INTERNAL TO IC PHASE1 RS CS IL1 RS IL2 L1 RDCR1 RPCB1 VO RDCR2 RPCB2 ISEN1 When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. Idroop flows through resistor Rdroop and creates a voltage drop of V droop = R droop x I droop (EQ. 2) FIGURE 10. CURRENT BALANCING CIRCUIT Vdroop is the droop voltage required to implement load line. Changing Rdroop or scaling Idroop can both change the load line slope. Since Idroop also sets the overcurrent protection level, it is recommended to first scale Idroop based on OCP requirement, then select an appropriate Rdroop value to obtain the desired load line slope. The ISL62882 monitors individual phase average current by monitoring the ISEN1and ISEN2 voltages. Figure 10 shows the current balancing circuit recommended for ISL62882. Each phase node voltage is averaged by a low-pass filter consisting of Rs and Cs, and presented to the corresponding ISEN pin. Rs should be routed to inductor phase-node pad in order to eliminate the effect of phase node parasitic PCB DCR. Equations 5 and 6 give the ISEN pin voltages: V ISEN1 = ( R dcr1 + R pcb1 ) x I L1 V ISEN2 = ( R dcr2 + R pcb2 ) x I L2 (EQ. 5) (EQ. 6) Differential Sensing Figure 9 also shows the differential voltage sensing scheme. VCCSENSE and VSSSENSE are the remote voltage sensing signals from the processor die. A unity gain differential amplifier senses the VSSSENSE voltage and add it to the DAC output. The error amplifier regulates the inverting and the non-inverting input voltages to be equal as shown in Equation 4: VCC SENSE + V droop where Rdcr1 and Rdcr2 are inductor DCR; Rpcb1 and Rpcb2 are parasitic PCB DCR between the inductor output side pad and the output voltage rail; and IL1 and IL2 are inductor average currents. The ISL62882 will adjust the phase pulse-width relative to the other phase to make VISEN1 = VISEN2, thus to achieve IL1 = IL2, when there are Rdcr1 = Rdcr2 and Rpcb1 = Rpcb2. Using same components for L1 and L2 will provide a good match of Rdcr1 and Rdcr2. Board layout will determine Rpcb1 and Rpcb2. It is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that Rpcb1 = Rpcb2 . = V DAC + VSS SENSE (EQ. 3) Rewriting Equation 3 and substitution of Equation 2 gives VCC SENSE - VSS SENSE = V DAC - R droop x I droop (EQ. 4) Equation 4 is the exact equation required for load line implementation. The VCCSENSE and VSSSENSE signals come from the processor die. The feedback will be open circuit in the absence of the processor. As Figure 9 shows, it is recommended to add a "catch" resistor to feed the VR local output voltage back to the compensator, and add another "catch" resistor to connect the VR local output ground to the RTN pin. These resistors, typically 10~100, will provide voltage feedback if the system is powered up without a processor installed. ISEN2 Cs PHASE2 Rs Rs Rs Rs Cs V2p L2 Rdcr2 V2n Rpcb2 IL2 VO INTERNAL TO IC ISEN1 L1 PHASE1 V1p IL1 Rdcr1 V1n Rpcb 1 FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT Sometimes, it is difficult to implement symmetrical layout. For the circuit Figure 10 shows, asymmetric layout causes different Rpcb1 and Rpcb2 thus current imbalance. Figure 11 shows a differential-sensing current balancing circuit recommended for ISL62882. The current sensing traces 14 FN6890.0 April 1, 2009 ISL62882, ISL62882B should be routed to the inductor pads so they only pick up the inductor DCR voltage. Each ISEN pin sees the average voltage of two sources: its own phase inductor phase-node pad, and the other phase inductor output side pad. Equations 7 and 8 give the ISEN pin voltages: V ISEN1 = V 1p + V 2n V ISEN2 = V 2p + V 1n (EQ. 7) (EQ. 8) Rep Rate = 10kHz The ISL62882 will make VISEN1 = VISEN2. So there are: V 1p + V 2n = V 2p + V 1n (EQ. 9) Rep Rate = 25kHz Rewriting Equation 9 gives: V 1p - V 1n = V 2p - V 2n (EQ. 10) Therefore: R dcr1 x I L1 = R dcr2 x I L2 (EQ. 11) Rep Rate = 50kHz Current balancing (IL1 = IL2) will be achieved when there is Rdcr1 = Rdcr2. Rpcb1 and Rpcb2 will not have any effect. Since the slave ripple capacitor voltages mimic the inductor currents, R3TM modulator can naturally achieve excellent current balancing during steady state and dynamic operations. Figure 12 shows current balancing performance of the ISL62882 evaluation board with load transient of 15A/50A at different rep rates. The inductor currents follow the load current dynamic change with the output capacitors supplying the difference. The inductor currents can track the load current well at a low rep rate, but cannot keep up when the rep rate gets into the hundred-kHz range, where it's out of the control loop bandwidth. The controller achieves excellent current balancing in all cases. Rep Rate = 100kHz Rep Rate = 200kHz FIGURE 12. ISL62882 EVALUATION BOARD CURRENT BALANCING DURING DYNAMIC OPERATION. Ch1: IL1, Ch2: IIoad, Ch3: IL2 15 FN6890.0 April 1, 2009 ISL62882, ISL62882B CCM Switching Frequency The Rfset resistor between the COMP and the VW pins sets the sets the VW windows size, therefore sets the switching frequency. When the ISL62882 is in continuous conduction mode (CCM), the switching frequency is not absolutely constant due to the nature of the R3TM modulator. As explained in the "Multiphase R3TM Modulator" on page 10, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. On the other hand, the switching frequency is relatively constant at steady state. Variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. The variation is usually less than 15% and doesn't have any significant effect on output voltage ripple magnitude. Equation 12 gives an estimate of the frequency-setting resistor Rfset value. 8k Rfset gives approximately 300kHz switching frequency. Lower resistance gives higher switching frequency. R fset ( k ) = ( Period ( s ) - 0.29 ) x 2.65 (EQ. 12) the VID command voltage, the dv/dt moderates to prevent overshoot. Geyserville-III transitions commands one LSB VID step (12.5mV) every 2.5s, controlling the effective dv/dt at 5mv/s. The ISL62882 is capable of 5mV/s slew rate. When the ISL62882 is in DE mode, it will actively drive the output voltage up when the VID changes to a higher value. It'll resume DE mode operation after reaching the new voltage level. If the load is light enough to warrant DCM, it will enter DCM after the inductor current has crossed zero for four consecutive cycles. The ISL62882 will remain in DE mode when the VID changes to a lower value. The output voltage will decay to the new value and the load will determine the slew rate. The ISL62882 employes a smart strategy to provide excellent transient response in 1-phase DE for the condition of PSI# = 0 and DPRSLPVR = 0, when there is still stringent transient response requirement. The output voltage may overshoot during load release response and reach its peak when the inductor current reaches zero. LGATE will then turn off and the output voltage will only be pulled down by the load. The duration of the overshoot may become long enough to violate the IMVP-6.5TM specifications. To minimize the overshoot duration, the ISL62882 keeps LGATE1 on after the inductor reaches zero to quickly pull down the output voltage. The ISL62882 monitors the COMP pin voltage to determine when the overshoot ends. The COMP pin voltage stays at the low clamp voltage during the output voltage overshoot, and leaves it when the output voltage is back within regulation. The ISL62882 resumes 1-phase DE operation when the COMP pin voltage leaves the low clamp voltage. When DPRSLPVR signal is high, indicating CPU deeper sleep state, there is no stringent transient response requirement. The ISL62882 will not use the above strategy and stay in DE all the time for maximum efficiency benefit. During load insertion response, the Fast Clock function increases the PWM pulse response speed. The ISL62883 monitors the VSEN pin voltage and compares it to 100ns-filtered version. When the unfiltered version is 20mV below the filtered version, the controller knows there is a fast voltage dip due to load insertion, hence issues an additional master clock signal to deliver a PWM pulse immediately. The R3TM modulator intrinsically has voltage feed-forward. The output voltage is insensitive to a fast slew rate input voltage change. Phase Count Configurations The ISL62882 can be configured for 2- or 1-phase operation. For 1-phase configuration, tie the ISEN2 pin to 5V. In this configuration, only phase-1 is active. Modes of Operation TABLE 2. ISL62882 MODES OF OPERATION CONFIGURATION 2-phase Configuration PSI# 0 0 1 1 1-phase Configuration 0 0 1 1 DPRSLPVR 0 1 0 1 0 1 0 1 OPERATIONAL MODE 1-phase DE 1-phase DE 2-phase CCM 1-phase DE 1-phase CCM 1-phase DE 1-phase CCM 1-phase DE Table 2 shows the ISL62882 operational modes, programmed by the logic status of the PSI# and DPRSLPVR pins. In 2-phase configuration, the ISL62882 enters 1-phase DE for PSI# = 0 or DPRSLPVR = 0. It drops phase 2 and reduces the overcurrent and the way-overcurrent protection levels to 1/2 of the initial values. In 1-phase configuration, the ISL62882 does not change the operational mode when the PSI# signal changes status. It enters 1-phase DE mode when DLPRSLPVR = 1. Protections The ISL62882 provides over-current, current-balance, undervoltage, overvoltage, and over-temperature protections. The ISL62882 determines over-current protection (OCP) by comparing the average value of the droop current Idroop with an internal current source threshold. It declares OCP when Idroop is above the threshold for 120s. A resistor Rcomp from Dynamic Operation The ISL62882 responds to VID changes by slewing to the new voltage at 5mV/s slew rate. As the output approaches 16 FN6890.0 April 1, 2009 ISL62882, ISL62882B the COMP pin to GND programs the OCP current source threshold, as Table 3 shows. It is recommended to use the nominal Rcomp value. The ISL62882 detects the Rcomp value at the beginning of start-up, and sets the internal OCP threshold accordingly. It remembers the Rcomp value until the VR_ON signal drops below the POR threshold. TABLE 3. ISL62882 OCP THRESHOLD Rcomp MIN (k) NOMINAL (k) none 320 210 155 104 78 62 45 400 235 165 120 85 66 50 MAX (k) none 480 260 175 136 92 70 55 OCP THRESHOLD (A) 1-PHASE Mode 20 22.7 20.7 18 20 22.7 20.7 18 2-PHASE Mode 40 45.3 41.3 36 37.33 38.7 42.7 44 The second level of overvoltage protection is different. If the output voltage exceeds 1.55V, the ISL62882 will immediately declare an OV fault, dessert PGOOD, and turn on the low-side power MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below 0.85V when all power MOSFETs are turned off. If the output voltage rises above 1.55V again, the protection process is repeated. This behavior provides the maximum amount of protection against shorted high-side power MOSFETs while preventing output ringing below ground. Resetting VR_ON cannot clear the 1.55V OVP. Only resetting VDD will clear it. The 1.55V OVP is active all the time when the controller is enabled, even if one of the other faults have been declared. This ensures that the processor is protected against high-side power MOSFET leakage while the MOSFETs are commanded off. The ISL62882 has a thermal throttling feature. If the voltage on the NTC pin goes below the 1.18V OT threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system. No other action is taken within the ISL62882 in response to NTC pin voltage. Table 4 summarizes the fault protections TABLE 4. FAULT PROTECTION SUMMARY FAULT DURATION BEFORE PROTECTION PROTECTION ACTION 120s <2s The default OCP threshold is the value when Rcomp is not populated. It is recommended to scale the droop current Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary. For overcurrent condition above 2.5x the OCP level, the PWM outputs will immediately shut off and PGOOD will go low to maximize protection. This protection is also referred to as way-over-current protection or fast-overcurrent protection, for short-circuit protections. The ISL62882 monitors the ISEN pin voltages to determine current-balance protection. If the ISEN pin voltage difference is greater than 9mV for 1ms, the controller will declare a fault and latch off. The ISL62882 will declare under-voltage (UV) fault and latch off if the output voltage is less than the VID set value by 300mV or more for 1ms. It'll turn off the PWM outputs and dessert PGOOD. The ISL62882 has two levels of overvoltage protections. The first level of overvoltage protection is referred to as PGOOD overvoltage protection. If the output voltage exceeds the VID set value by +200mV for 1ms, the ISL62882 will declare a fault and dessert PGOOD. The ISL62882 takes the same actions for all of the above fault protections: desertion of PGOOD and turn-off of the high-side and low-side power MOSFETs. Any residual inductor current will decay through the MOSFET body diodes. These fault conditions can be reset by bringing VR_ON low or by bringing VDD below the POR threshold. When VR_ON and VDD return to their high operating levels, a soft-start will occur. FAULT TYPE Overcurrent Way-Overcurrent (2.5xOC) FAULT RESET PWM tri-state, VR_ON toggle or PGOOD VDD toggle latched low Overvoltage +200mV 1ms Undervoltage -300mV Phase Current Unbalance Overvoltage 1.55V Immediately Low-side VDD toggle MOSFET on until Vcore <0.85V, then PWM tri-state, PGOOD latched low. 1ms N/A Over-Temperature Current Monitor The ISL62882 provides the current monitor function. The IMON pin outputs a high-speed analog current source that is 3 times of the droop current flowing out of the FB pin. Thus Equation 13: I IMON = 3 x I droop (EQ. 13) As Figures 1 and 2 show, a resistor Rimon is connected to the IMON pin to convert the IMON pin current to voltage. A capacitor can be paralleled with Rimon to filter the voltage 17 FN6890.0 April 1, 2009 ISL62882, ISL62882B information. The IMVP-6.5TM specification requires that the IMON voltage information be referenced to VSSSENSE. The IMON pin voltage range is 0V to 1.1V. A clamp circuit prevents the IMON pin voltage from going above 1.1V. MOSFET and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low-side MOSFET body diode conducts for approximately 40ns to minimize the body diode-related loss. FB2 Function The FB2 function is only available when the ISL62882 is in 2-phase configuration. CONTROLLER IN 2-PHASE MODE C2 C1 R2 C3.1 FB2 C3.2 CONTROLLER IN 1-PHASE MODE C2 C1 R2 C3.1 FB2 C3.2 Overshoot Reduction Function The ISL62882 has an optional overshoot reduction function. Using RBIAS = 47k enables this function and using RBIAS = 147k disables this function. When a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. The inductor current freewheels through the low-side MOSFET during this period of time. The overshoot reduction function turns off the low-side MOSFET during the output voltage overshoot, forcing the inductor current to freewheel through the low-side MOSFET body diode. Since the body diode voltage drop is much higher than MOSFET Rdson voltage drop, more energy is dissipated on the low-side MOSFET therefore the output voltage overshoot is lower. If the overshoot reduction function is enabled, the ISL62882 monitors the COMP pin voltage to determine the output voltage overshoot condition. The COMP voltage will fall and hit the clamp voltage when the output voltage overshoots. The ISL62882 will turn off LGATE1 and LGATE2 when COMP is being clamped. All the low-side MOSFETs in the power stage will be turned off. When the output voltage has reached its peak and starts to come down, the COMP voltage starts to rise and is no longer clamped. The ISL62882 will resume normal PWM operation. When PSI# is low, indicating a low power state of the CPU, the controller will disable the overshoot reduction function as large magnitude transient event is not expected and overshoot is not a concern. While the overshoot reduction function reduces the output voltage overshoot, energy is dissipated on the low-side MOSFET, causing additional power loss. The more frequent transient event, the more power loss dissipated on the lowside MOSFET. The MOSFET may face severe thermal stress when transient events happen at a high repetitive rate. User discretion is advised when this function is enabled. R3 R1 R3 R1 VSEN FB VREF E/A COMP VSEN FB VREF E/A COMP FIGURE 13. FB2 FUNCTION IN 2-PHASE MODE Figure 13 shows the FB2 function. A switch (called FB2 switch) turns on to short the FB and the FB2 pins when the controller is in 2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving as part of the compensator. When the controller enters 1-phase mode, the FB2 switch turns off, removing C3.2 and leaving only C3.1 in the compensator. The compensator gain will increase with the removal of C3.2. By properly sizing C3.1 and C3.2, the compensator cab be optimal for both 2-phase mode and 1-phase mode. When the FB2 switch is off, C3.2 is disconnected from the FB pin. However, the controller still actively drives the FB2 pin voltage to follow the FB pin voltage such that C3.2 voltage always follows C3.1 voltage. When the controller turns on the FB2 switch, C3.2 will be reconnected to the compensator smoothly. The FB2 function ensures excellent transient response in both 2-phase mode and 1-phase mode. If one decides not to use the FB2 function, simply populate C3.1 only. Adaptive Body Diode Conduction Time Reduction In DCM, the controller turns off the low-side MOSFET when the inductor current approaches zero. During on-time of the low-side MOSFET, phase voltage is negative and the amount is the MOSFET Rdson voltage drop, which is proportional to the inductor current. A phase comparator inside the controller monitors the phase voltage during on-time of the low-side MOSFET and compares it with a threshold to determine the zero-crossing point of the inductor current. If the inductor current has not reached zero when the low-side MOSFET turns off, it'll flow through the low-side MOSFET body diode, causing the phase node to have a larger voltage drop until it decays to zero. If the inductor current has crossed zero and reversed the direction when the low-side MOSFET turns off, it'll flow through the high-side MOSFET body diode, causing the phase node to have a spike until it decays to zero. The controller continues monitoring the phase voltage after turning off the low-side 18 Key Component Selection RBIAS The ISL62882 uses a resistor (1% or better tolerance is recommended) from the RBIAS pin to GND to establish highly accurate reference current sources inside the IC. Using RBIAS = 47k enables the overshoot reduction function and using RBIAS = 147k disables this function. Do not connect any other components to this pin. Do not connect any capacitor to the RBIAS pin as it will create instability. FN6890.0 April 1, 2009 ISL62882, ISL62882B Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor. frequency-domain relationship between inductor total current Io(s) and Cn voltage VCn(s) R ntcnet DCR V Cn ( s ) = ----------------------------------------- x ------------- x I o ( s ) x A cs ( s ) R sum N R ntcnet + ------------- N ( R ntcs + R ntc ) x R p R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p s 1 + -----L A cs ( s ) = ---------------------s 1 + ----------- sns DCR L = ------------L (EQ. 14) Ris and Cis As Figures 1 and 2 show, the ISL62882 needs the Ris - Cis network across the ISUM+ and the ISUM- pins to stabilize the droop amplifier. The preferred values are Ris = 82.5 and Cis = 0.01F. Slight deviations from the recommended values are acceptable. Large deviations may result in instability. Inductor DCR Current-Sensing Network Phase1 Phase2 Rsum Rsum ISUM+ (EQ. 15) (EQ. 16) (EQ. 17) (EQ. 18) L L Rntcs Rp Cn 1 sns = -------------------------------------------------------R sum R ntcnet x -------------N ------------------------------------------ x C n R sum R ntcnet + -------------N Vcn ISUM- where N is the number of phases. Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, giving higher reading of the inductor DC current. The NTC Rntc values decreases as its temperature decreases. Proper selections of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn represent the inductor total DC current over the temperature range of interest. There are many sets of parameters that can properly temperature-compensate the DCR change. Since the NTC network and the Rsum resistors form a voltage divider, Vcn is always a fraction of the inductor DCR voltage. It is recommended to have a higher ratio of Vcn to the inductor DCR voltage, so the droop circuit has higher signal level to work with. A typical set of parameters that provide good temperature compensation are: Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k and Rntc = 10k (ERT-J1VR103J). The NTC network parameters may need to be fine tuned on actual boards. One can apply full load DC current and record the output voltage reading immediately; then record the output voltage reading again when the board has reached the thermal steady state. A good NTC network can limit the output voltage drift to within 2mV. It is recommended to follow the Intersil evaluation board layout and current-sensing network parameters to minimize engineering time. VCn(s) also needs to represent real-time Io(s) for the controller to achieve good transient response. Transfer function Acs(s) has a pole sns and a zero L. One needs to match L and sns so Acs(s) is unity gain at all frequencies. DCR DCR Rntc Ro Ro Ri Io FIGURE 14. DCR CURRENT-SENSING NETWORK Figure 14 shows the inductor DCR current-sensing network for a 2-phase solution. An inductor current flows through the DCR and creates a voltage drop. Each inductor has two resistors in Rsum and Ro connected to the pads to accurately sense the inductor current by sensing the DCR voltage drop. The Rsum and Ro resistors are connected in a summing network as shown, and feed the total current information to the NTC network (consisting of Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative temperature coefficient (NTC) thermistor, used to temperature-compensate the inductor DCR change. The inductor output side pads are electrically shorted in schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. It is recommended to use 1~10 Ro to create quality signals. Since Ro value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. The summed inductor current information is presented to the capacitor Cn. Equations 14 thru 18 describe the 19 FN6890.0 April 1, 2009 ISL62882, ISL62882B By forcing L equal to sns and solving for the solution, Equation 19 gives Cn value. L C n = -------------------------------------------------------------R sum R ntcnet x -------------N ------------------------------------------ x DCR R sum R ntcnet + -------------N (EQ. 19) io iL V o RING BACK FIGURE 18. OUTPUT VOLTAGE RING BACK PROBLEM io V o FIGURE 15. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS ISUM+ Rntcs Rp Rntc Cn.1 Cn.2 Rn Optional Ri ISUM- Vcn io V o FIGURE 16. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL Rip Cip Optional FIGURE 19. OPTIONAL CIRCUITS FOR RING BACK REDUCTION io V o FIGURE 17. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE For example, given N = 2, Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 0.88m and L = 0.36H, Equation 19 gives Cn = 0.294F. Assuming the compensator design is correct, Figure 15 shows the expected load transient response waveforms if Cn is correctly selected. When the load current Icore has a square change, the output voltage Vcore also has a square response. If Cn value is too large or too small, VCn(s) will not accurately represent real-time Io(s) and will worsen the transient response. Figure 16 shows the load transient response when Cn is too small. Vcore will sag excessively upon load insertion and may create a system failure. Figure 17 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the CPU reliability. Figure 18 shows the output voltage ring back problem during load transient response. The load current io has a fast step change, but the inductor current iL cannot accurately follow. Instead, iL responds in first order system fashion due to the nature of current loop. The ESR and ESL effect of the output capacitors makes the output voltage Vo dip quickly upon load current change. However, the controller regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore it pulls Vo back to the level dictated by iL, causing the ring back problem. This phenomenon is not observed when the output capacitor have very low ESR and ESL, such as all ceramic capacitors. Figure 19 shows two optional circuits for reduction of the ring back. Rip and Cip form an R-C branch in parallel with Ri, providing a lower impedance path than Ri at the beginning of io change. Rip and Cip do not have any effect at steady state. Through proper selection of Rip and Cip values, idroop can resemble io rather than iL, and Vo will not ring back. The recommended value for Rip is100. Cip should be determined through tuning the load transient response waveforms on an actual board. The recommended range for Cip is 100pF~2000pF. Cn is the capacitor used to match the inductor time constant. It usually takes the parallel of two (or more) capacitors to get the desired value. Figure 19 shows that two capacitors Cn.1 and Cn.2 are in parallel. Resistor Rn is an optional FN6890.0 April 1, 2009 20 ISL62882, ISL62882B component to reduce the Vo ring back. At steady state, Cn.1+Cn.2 provides the desired Cn capacitance. At the beginning of io change, the effective capacitance is less because Rn increases the impedance of the Cn.1 branch. As Figure 16 explains, Vo tends to dip when Cn is too small, and this effect will reduce the Vo ring back. This effect is more pronounced when Cn.1 is much larger than Cn.2. It is also more pronounced when Rn is bigger. However, the presence of Rn increases the ripple of the Vn signal if Cn.2 is too small. It is recommended to keep Cn.2 greater than 2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values should be determined through tuning the load transient response waveforms on an actual board. variation over-temperature, so there is no need for the NTC network. The recommended values are Rsum = 1k and Cn = 5600pF. Overcurrent Protection Refer to Equation 1 on page 14 and Figures 9, 14 and 20, resistor Ri sets the droop current Idroop. Table 3 shows the internal OCP threshold. It is recommended to design Idroop without using the Rcomp resistor. For example, the OCP threshold is 40A for 2-phase solution. We will design Idroop to be 34.3A at full load, so the OCP trip level is 1.16x of the full load current. For inductor DCR sensing, Equation 23 gives the DC relationship of Vcn(s) and Io(s). R ntcnet DCR V Cn = ------------------------------------------ x ------------- x I o N R sum R ntcnet + ------------- N Resistor Current-Sensing Network PHASE1 PHASE2 L L (EQ. 23) DCR DCR RSUM RSUM ISUM+ Substitution of Equation 23 into Equation 1 gives R ntcnet DCR 2 I droop = ---- x ------------------------------------------ x ------------- x I o N R sum Ri R ntcnet + -------------N (EQ. 24) RSEN RSEN RO RO VCN CN RI ISUM- Therefore 2R ntcnet x DCR x I o R i = --------------------------------------------------------------------------------R sum R xI N x ntcnet + ------------- N droop (EQ. 25) IO FIGURE 20. RESISTOR CURRENT-SENSING NETWORK Substitution of Equation 15 and application of the OCP condition in Equation 25 gives ( R ntcs + R ntc ) x R p 2 x ---------------------------------------------------- x DCR x I omax R ntcs + R ntc + R p R i = ---------------------------------------------------------------------------------------------------------------------------( R ntcs + R ntc ) x R p R sum N x ---------------------------------------------------- + -------------- x I droopmax N R ntcs + R ntc + R p Figure 20 shows the resistor current-sensing network for a 2-phase solution. Each inductor has a series current-sensing resistor Rsen. Rsum and Ro are connected to the Rsen pads to accurately capture the inductor current information. The Rsum and Ro resistors are connected to capacitor Cn. Rsum and Cn form a a filter for noise attenuation. Equations 20 thru 22 give VCn(s) expression R sen V Cn ( s ) = ------------- x I o ( s ) x A Rsen ( s ) N (EQ. 20) (EQ. 26) where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given N = 2, Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 0.88m, Iomax = 51A and Idroopmax = 34.3A, Equation 26 gives Ri = 998. For resistor sensing, Equation 27 gives the DC relationship of Vcn(s) and Io(s). R sen V Cn = ------------- x I o N (EQ. 27) 1 A Rsen ( s ) = ---------------------s 1 + ----------- sns (EQ. 21) 1 Rsen = ---------------------------R sum -------------- x C n N (EQ. 22) Substitution of Equation 27 into Equation 1 gives 2 R sen I droop = ---- x ------------- x I o N Ri (EQ. 28) Transfer function ARsen(s) always has unity gain at DC. Current-sensing resistor Rsen value will not have significant 21 FN6890.0 April 1, 2009 ISL62882, ISL62882B Therefore 2R sen x I o R i = --------------------------N x I droop (EQ. 29) Rewriting Equation 33 gives Io I droop = ------------------ x LL R droop (EQ. 35) Substitution of Equation 29 and application of the OCP condition in Equation 25 gives 2R sen x I omax R i = --------------------------------------N x I droopmax (EQ. 30) Substitution of Equation 35 into Equation 34 gives 3I o x LL V Rimon = --------------------- x R imon R droop (EQ. 36) where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given N = 2, Rsen = 1m, Iomax = 51A and Idroopmax = 34.3A, Equation 30 gives Ri = 1.487k. A resistor from COMP to GND can adjust the internal OCP threshold, providing another dimension of fine-tune flexibility. Table 3 shows the detail. It is recommended to scale Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary Rewriting Equation 36 and application of full load condition gives V Rimon x R droop R imon = ---------------------------------------------3I o x LL (EQ. 37) For example, given LL = 1.9m, Rdroop = 2.825k, VRimon = 963mV at Iomax = 51A, Equation37 gives Rimon = 9.358k. A capacitor Cimon can be paralleled with Rimon to filter the IMON pin voltage. The RimonCimon time constant is the user's choice. It is recommended to have a time constant long enough such that switching frequency ripples are removed. Load Line Slope Refer to Figure 9. For inductor DCR sensing, substitution of Equation 24 into Equation 2 gives the load line slope expression V droop 2R droop R ntcnet DCR LL = ------------------ = ---------------------- x ------------------------------------------ x ------------N Io Ri R sum R ntcnet + -------------N (EQ. 31) Compensator Figure 15 shows the desired load transient response waveforms. Figure 21 shows the equivalent circuit of a voltage regulator (VR) with the droop function. A VR is equivalent to a voltage source (= VID) and output impedance Zout(s). If Zout(s) is equal to the load line slope LL, i.e. constant output impedance, in the entire frequency range, Vo will have square response when Io has a square change. For resistor sensing, substitution of Equation 28 into Equation 2 gives the load line slope expression 2R sen x R droop V droop LL = ------------------ = -----------------------------------------N x Ri Io (EQ. 32) Zout(s) = LL VID VR io LOAD Vo Substitution of Equation 25 and rewriting Equation 31, or substitution of Equation 29 and rewriting Equation 32 give the same result in Equation 33 Io R droop = ---------------- x LL I droop (EQ. 33) FIGURE 21. VOLTAGE REGULATOR EQUIVALENT CIRCUIT One can use the full load condition to calculate Rdroop. For example, given Iomax = 51A, Idroopmax = 38.8A and LL = 1.9m, Equation 33 gives Rdroop = 2.825k. It is recommended to start with the Rdroop value calculated by Equation 33, and fine tune it on the actual board to get accurate load line slope. One should record the output voltage readings at no load and at full load for load line slope calculation. Reading the output voltage at lighter load instead of full load will increase the measurement error. Intersil provides a Microsoft Excel-based spreadsheet to help design the compensator and the current sensing network, so the VR achieves constant output impedance as a stable system. Figure 24 shows a screenshot of the spreadsheet. A VR with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. However, neither loop alone is sufficient to describe the entire system. The spreadsheet shows two loop gain transfer functions, T1(s) and T2(s), that describe the entire system. Figure 22 conceptually shows T1(s) measurement set-up and Figure 23 conceptually shows T2(s) measurement set-up. The VR senses the inductor current, multiplies it by a gain of the load line slope, then Current Monitor Refer to Equation 13 for the IMON pin current expression. Refer to Figures 1 and 2, the IMON pin current flows through Rimon. The voltage across Rimon is V Rimon = 3 x I droop x R imon (EQ. 34) 22 FN6890.0 April 1, 2009 ISL62882, ISL62882B adds it on top of the sensed output voltage and feeds it to the compensator. T(1) is measured after the summing node, and T2(s) is measured in the voltage loop before the summing node. The spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) can be actually measured on an ISL62882 regulator. T1(s) is the total loop gain of the voltage loop and the droop loop. It always has a higher crossover frequency than T2(s) and has more meaning of system stability. T2(s) is the voltage loop gain with closed droop loop. It has more meaning of output voltage response. Design the compensator to get stable T1(s) and T2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. Loop Gain= L Q1 Vo C out V in Gate Driver Q2 io Load Line Slope 20ohm Mod. Comp EA VID Isolation Transformer Channel B Channel A Channel A Network Analyzer Channel B Excitation Output FIGURE 22. LOOP GAIN T1(s) MEASUREMENT SET-UP L Q1 Vo C out V in Gate Driver Q2 io Load Line Slope 20ohm Mod. Comp EA VID Isolation Transformer Loop Gain= Channel B Channel A Channel A Network Analyzer Channel B Excitation Output FIGURE 23. LOOP GAIN T2(s) MEASUREMENT SET-UP 23 FN6890.0 April 1, 2009 Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5 Current Sensing Network Parameters FIGURE 24. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET 24 1.15 Output Impedance, Gain Curve Jia Wei, jwei@intersil.com, 919-405-3605 Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak". 2. Green cells require user input Compensator Parameters Operation Parameters Controller Part Number: ISL6288x s s Ki i 1 1 Phase Number: 2 2 f z1 2 f z2 AV ( s ) Vin: 12 volts s s Vo: 1.15 volts s1 1 2 f p1 2 f p2 Full Load Current: 50 Amps Estimated Full-Load Efficiency: 87 % Number of Output Bulk Capacitors: 3 Recommended Value User-Selected Value Capacitance of Each Output Bulk Capacitor: 470 uF R1 2.870 k R1 2.87 k ESR of Each Output Bulk Capacitor: 4.5 m ESL of Each Output Bulk Capacitor: 0.6 nH R2 387.248 k R2 412 k Number of Output Ceramic Capacitors: 30 R3 0.560 k R3 0.562 k Capacitance of Each Output Ceramic Capacitor: 10 uF C1 188.980 pF C1 150 pF C2 498.514 pF C2 390 pF ESR of Each Output Ceramic Capacitor: 3m ESL of Each Output Ceramic Capacitor: 3 nH C3 32.245 pF C3 32 pF Switching Frequency: 300 kHz Use User-Selected Value (Y/N)? N Inductance Per Phase: 0.36 uH CPU Socket Resistance: 0.9 m Performance and Stability Desired Load-Line Slope: 1.9 m Desired ISUM- Pin Current at Full Load: 33.1 uA T1 Bandwidth: 190kHz T2 Bandwidth: 52kHz (This sets the over-current protection level) T1 Phase Margin: 63.4 T2 Phase Margin: 94.7 Changing the settings in red requires deep understanding of control loop design Place the 2nd compensator pole fp2 at: 1.9 xfs (Switching Frequency) Tune K i to get the desired loop gain bandwidth Tune the compensator gain factor K i: (Recommended K i range is 0.8~2) Operation Parameters Inductor DCR 0.88 m Rsum 3.65 k Rntc 10 k Rntcs 2.61 k Rp 11 k Recommended Value Cn 0.294 uF Ri 1014.245 User Selected Value Cn 0.294 uF Ri 1000 ISL62882, ISL62882B Loop Gain, Gain Curve Loop Gain, Phase Curve Output Impedance, Phase Curve FN6890.0 April 1, 2009 ISL62882, ISL62882B Optional Slew Rate Compensation Circuit For 1-Tick VID Transition Rdroop Rvid FB Ivid Idroop_vid COMP E/A Cvid Optional When Vcore increases, the time domain expression of the induced Idroop change is -------------------------- C out x LL dV core C x LL I droop ( t ) = ------------------------- x ------------------ x 1 - e out dt R droop -t (EQ. 38) Vcore where Cout is the total output capacitance. In the mean time, the Rvid-Cvid branch current Ivid time domain expression is ------------------------------- dV fb R xC vid I vid ( t ) = C vid x ------------ x 1 - e vid dt -t (EQ. 39) VDAC DAC VIDs RTN VID<0:6> VSSSENSE It is desired to let Ivid(t) cancel Idroop_vid(t). So there are dV fb C out x LL dV core C vid x ------------ = ------------------------- x -----------------dt dt R droop (EQ. 40) Internal to IC X1 VSS and VID<0:6> R vid x C vid = C out x LL (EQ. 41) Vfb The result is R vid = R droop (EQ. 42) Ivid and dV core C out x LL -----------------dt C vid = ------------------------- x -----------------R droop dV fb -----------dt (EQ. 43) Vcore Idroop_vid FIGURE 25. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR1-TICK VID TRANSITION For example: given LL = 1.9m, Rdroop = 2.87k, Cout = 1710F, dVcore/dt = 5mV/s and dVfb/dt = 15mV/s, Equation 42 gives Rvid=2.87k and Equation 43 gives Cvid = 377pF. It's recommended to select the calculated Rvid value and start with the calculated Cvid value and tweak it on the actual board to get the best performance. During normal transient response, the FB pin voltage is held constant, therefore is virtual ground in small signal sense. The Rvid - Cvid network is between the virtual ground and the real ground, and hence has no effect on transient response. During a large VID transition, the DAC steps through the VIDs at a controlled slew rate of 2.5s per tick (12.5mV), controlling output voltage Vcore slew rate at 5mV/s. Figure 25 shows the waveforms of 1-tick VID transition. During 1-tick VID transition, the DAC output changes at approximately 15mV/s slew rate, but the DAC cannot step through multiple VIDs to control the slew rate. Instead, the control loop response speed determines Vcore slew rate. Ideally, Vcore will follow the FB pin voltage slew rate. However, the controller senses the inductor current increase during the up transition, as the Idroop_vid waveform shows, and will droop the output voltage Vcore accordingly, making Vcore slew rate slow. Similar behavior occurs during the down transition. To control Vcore slew rate during 1-tick VID transition, one can add the Rvid-Cvid branch, whose current Ivid cancels Idroop_vid. 25 FN6890.0 April 1, 2009 ISL62882, ISL62882B Voltage Regulator Thermal Throttling 54A 64A SW1 NTC + VNTC RNTC Rs 1.24V SW2 1.20V INTERNAL TO ISL62882 + VR_TT# For example, given Panasonic NTC thermistor with B = 4700, the resistance will drop to 0.03322 of its nominal at +105C, and drop to 0.03956 of its nominal at +100C. If the required temperature hysteresis is +105C to +100C, the required resistance of NTC will be as shown in Equation 45: 2.96k ----------------------------------------------------- = 467k ( 0.03956 - 0.03322 ) (EQ. 45) Therefore, a larger value thermistor such as 470k NTC should be used. At +105C, 470k NTC resistance becomes (0.03322 x 470k) = 15.6k. With 60A on the NTC pin, the voltage is only (15.6k x 60A) = 0.937V. This value is much lower than the threshold voltage of 1.20V. Therefore, a regular resistor needs to be in series with the NTC. The required resistance can be calculated by Equation 46: 1.20V --------------- - 15.6k = 4.4k 60A (EQ. 46) FIGURE 26. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE OF THE ISL62882 Figure 26 shows the thermal throttling feature with hysteresis. An NTC network is connected between the NTC pin and GND. At low temperature, SW1 is on and SW2 connects to the 1.20V side. The total current flowing out of the NTC pin is 60A. The voltage on NTC pin is higher than threshold voltage of 1.20V and the comparator output is low. VR_TT# is pulled up by the external resistor. When temperature increases, the NTC thermistor resistance decreases so the NTC pin voltage drops. When the NTC pin voltage drops below 1.20V, the comparator changes polarity and turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low and sends the signal to start thermal throttle. There is a 6A current reduction on NTC pin and 40mV voltage increase on threshold voltage of the comparator in this state. The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature drops down, the NTC thermistor voltage will go up. If NTC voltage increases to above 1.24V, the comparator will flip back. The external resistance difference in these two conditions is shown in Equation 44: 1.24V 1.20V --------------- - --------------- = 2.96k 54A 60A (EQ. 44) 4.42k is a standard resistor value. Therefore, the NTC branch should have a 470k NTC and 4.42k resistor in series. The part number for the NTC thermistor is ERTJ0EV474J. It is a 0402 package. NTC thermistor will be placed in the hot spot of the board. Current Balancing Refer to Figures 1 and 2. The ISL62882 achieves current balancing through matching the ISEN pin voltages. Rs and Cs form filters to remove the switching ripple of the phase node voltages. It is recommended to use rather long RsCs time constant such that the ISEN voltages have minimal ripple and represent the DC current flowing through the inductors. Recommended values are Rs = 10k and Cs = 0.22F. Layout Guidelines Table 5 shows the layout considerations. The designators refer to the reference design shown in Figure.27. TABLE 5. LAYOUT CONSIDERATION PIN NAME GND LAYOUT CONSIDERATION Create analog ground plane underneath the controller and the analog signal processing components. Don't let the power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane. No special consideration No special consideration Place the RBIAS resistor (R16) in general proximity of the controller. Low impedance connection to the analog ground plane. No special consideration One needs to properly select the NTC thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. A regular resistor may need to be in series with the NTC thermistor to meet the threshold voltage values. EP 1 2 3 PGOOD PSI# RBIAS 4 VR_TT# 26 FN6890.0 April 1, 2009 ISL62882, ISL62882B TABLE 5. LAYOUT CONSIDERATION (Continued) PIN 5 NAME NTC LAYOUT CONSIDERATION The NTC thermistor (R9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. Usually it's placed close to phase-1 high-side MOSFET. Place the capacitor (C4) across VW and COMP in close proximity of the controller Place the compensator components (C3, C5, C6 R7, R11, R10 and C11) in general proximity of the controller. A capacitor (C9) decouples it to GND. Place it in general proximity of the controller. A capacitor (C10) decouples it to GND. Place it in general proximity of the controller. Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling. 25 Place the current sensing circuit in general proximity of the controller. Place C82 very close to the controller. Place NTC thermistors R42 next to phase-1 inductor (L1) so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signals traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71 to the phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and R72 to the phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. 26 27 22 23 24 VSSP1 PIN 19 TABLE 5. LAYOUT CONSIDERATION (Continued) NAME BOOT1 LAYOUT CONSIDERATION Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE1 trace to the phase-1 high-side MOSFET (Q2 and Q8) source pins instead of general phase1 node copper. 20 21 UGATE1 PHASE1 6 7 8 9 10 11 12 13 14 15 VW COMP FB FB2 ISEN2 ISEN1 VSEN RTN ISUMISUM+ Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or LGATE1b getting close. Recommend routing VSSP1 to the phase-1 low-side MOSFET (Q3 and Q9) source pins instead of general power ground plane for better performance. LGATE1a VCCP LGATE2 VSSP2 A capacitor (C22) decouples it to GND. Place it in close proximity of the controller. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing VSSP2 to the phase-2 low-side MOSFET (Q5 and Q1) source pins instead of general power ground plane for better performance. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE2 trace to the phase-2 high-side MOSFET (Q4 and Q10) source pins instead of general phase-2 node copper. Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. No special consideration. No special consideration. 28 29 PHASE2 UGATE2 30 BOOT2 31~37 38 39 40 VID0~6 VR_ON DPRSLPVR No special consideration. CLK_EN# No special consideration. Inductor Inductor Other Phase Node Minimize phase node copper area. Don't let the phase node copper overlap with/getting close to other sensitive traces. Cut the power ground plane to avoid overlapping with phase node copper. Other Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and Q9). Vias Current-Sensing Traces 16 17 18 VDD VIN IMON Current-Sensing Traces A capacitor (C16) decouples it to GND. Place it in close proximity of the controller. A capacitor (C17) decouples it to GND. Place it in close proximity of the controller. Place the filter capacitor (C21) close to the CPU. 27 FN6890.0 April 1, 2009 8 7 6 5 4 IN 3 2 1 VIN C24 56UF C25 56UF C28 10UF C34 10UF IRF7821 IRF7821 Q4 L2 C39 C52 C57 Q10 D OUT D C44 470UF 470UF 0 0.22UF R65 R72 1.91K OUT OUT OUT C40 C41 C42 C43 C47 10UF 10UF 10UF 10UF 10UF VSUMC49 C50 C53 C54 C55 C48 C56 IN CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 C27 10UF C33 R12 10UF 10UF 10UF VR_TT# OUT ---- OPTIONAL RBIAS PHASE2 U6 LGATE2 VCCP LGATE1B LGATE1A VSSP1 PHASE1 0 0.22UF Q3 IN R16 R8 147K R9 VR_TT# VSSP2 NTC VW COMP FB R10 C11 FB2 ISEN2 EP ISL62882HRZ PSI# UGATE2 Q2 Q8 L1 C59 C60 C61 C62 10UF C63 10UF 10UF 10UF 10UF C4 8.06K ------R4 DNP ------R6 ---- 1000PF TBD +5V NTC TBD Q9 R63 R71 C65 C66 C67 C68 C69 10UF 10UF 10UF VSUM+ ISEN1 VSUM- C71 C72 C73 C74 C75 C78 10UF 10UF 10UF 10UF ------------C83 R110 ISL62882, ISL62882B OPTIONAL ---ISEN2 IN ISEN1 IN C10 560PF 2.87K ------------- ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT UGATE1 LAYOUT R20 R37 1 R40 IN OUT IN NOTE: C9 0.22UF 0.22UF R50 9.31K C21 C16 1UF C17 0.22UF 0.22UF R26 C82 C18 R38 C15 C13 1000PF ----330PF ----- R18 10 0.01UF 82.5 C20 ---- ---- 0.1UF 1K ----------C81 R109 PLACE NEAR L1 -----> R42 R30 10K 2.61K NTC VSSSENSE IN 0.047UF 0.33UF 11K ---- R41 VCCSENSE IN ----C12 FIGURE 27. 2-PHASE REFERENCE DESIGN 0 0 +5V VIN IN IN IMON ROUTE UGATE1 TRACE IN PARALLEL WITH THE PHASE1 TRACE GOING TO THE SOURCE OF Q2 AND Q8 VSSSENSE VSUM+ VCORE IN R17 10 OPTIONAL ---- ROUTE LGATE1 TRACE IN PARALLEL WITH THE VSSP1 TRACE GOING TO THE SOURCE OF Q3 AND Q9 SAME RULE APPLIES TO OTHER PHASES A A IN VSUMTITLE: DATE: 1200PF 100 ----------OPTIONAL ISL62882 REFERENCE DESIGN 2-PHASE, DCR SENSING ENGINEER: JIA WEI 6 5 4 3 2 PAGE: 1 10UF 12/15/2008 1 OF 1 8 7 10UF B C22 1UF C3 10PF R11 R7 562 2.87K 390PF 10UF 10UF 10UF C6 C70 ---- 22PF 3.65K 10K R88 C5 1 10UF 10UF R56 C30 IRF7832 IRF7832 0.36UH C64 10UF 10UF C 499 PGOOD BOOT2 10UF IRF7821 IRF7821 VSUM+ ISEN2 PSI# +1.1V IN R19 10K 10UF PGOOD OUT 3.65K +3.3V IN 10K R90 R23 1 470UF VID0 IN VID1 IN VID2 IN VID3 IN VID4 IN VID5 IN VID6 IN VR_ON IN DPRSLPVR IN CLK_EN# OUT R57 IRF7832 IRF7832 Q5 Q11 DNP 28 C31 0.36UH VCORE C OUT OUT OUT 150PF 412K B FN6890.0 April 1, 2009 ISL62882, ISL62882B Reference Design Bill of Materials QTY 1 1 1 1 2 1 1 6 2 4 1 3 REFERENCE C11 C12 C13 C15 C16,C22 C18 C20 C21, C9, C10, C17, C30, C31 C24,C25 C27,C28,C33,C34 C3 C39, C52, C57 VALUE 390pF 330pF DESCRIPTION Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC SANYO GENERIC GENERIC PANASONIC KEMET GENERIC MURATA PANASONIC TDK GENERIC GENERIC GENERIC GENERIC GENERIC PART NUMBER H1045-00391-16V10 H1045-00331-16V10 H1045-00102-16V10 H1045-00103-16V10 H1045-00105-16V20 H1045-00334-16V10 H1045-00104-16V10 H1045-00224-16V10 25SP56M H1065-00106-25V20 H1045-00151-16V10 EEXSX0D471E4 T520V477M2R5A(1)E4R5 H1045-00102-16V10 SM0603 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC SM1206 SM0603 1000pF Multilayer Cap, 16V, 10% 0.01F 1F 0.33F 0.1F 0.22F Multilayer Cap, 16V, 10% 56F 10F 150pF 470F Radial SP Series Cap, 25V, 20% Multilayer Cap, 25V, 20% Multilayer Cap, 16V, 10% SPCAP, 2V, 4M POLYMER CAP, 2.5V, 4.5M Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 20% Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% 1 30 C4 C40-C43, C47-C50, C53-C56, C59-C75, C78 1000pF Multilayer Cap, 16V, 10% 10F Multilayer Cap, 6.3V, 20% GRM21BR61C106KE15L ECJ2FB0J106K C2012X5R0J106K SM0805 H1045-00220-16V10 H1045-00100-16V10 H1045-00122-16V10 H1045-00473-16V10 H1045-00561-16V10 MPCH1040LR36 ETQP4LR36AFC IRF7821 IRF7832 H2511-05620-1/16W1 H2511-01000-1/16W1 H2511-02871-1/16W1 H2511-02871-1/16W1 H2511-04990-1/16W1 H2511-01473-1/16W1 H2511-00100-1/16W1 H2511-01002-1/16W1 H2511-01911-1/16W1 H2511-082R5-1/16W1 H2511-00R00-1/16W1 H2511-01001-1/16W1 SM0603 SM0603 SM0603 SM0603 SM0603 1 1 1 1 1 2 C5 C6 C81 C82 C83 L1, L2 22pF 10pF Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% 1200pF Multilayer Cap, 16V, 10% 0.047F Multilayer Cap, 16V, 10% 560pF 0.36H Multilayer Cap, 16V, 10% NEC-TOKIN Inductor, Inductance 20%, DCR 7% PANASONIC N-Channel Power MOSFET N-Channel Power MOSFET IR IR GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC 10mmx10mm PWRPAKSO8 PWRPAKSO8 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 4 4 1 1 1 1 1 1 2 3 1 1 4 1 Q2, Q4, Q8, Q10 Q3, Q5, Q9, Q11 R10 R109 R11 R110 R12 R16 R17, R18 R19, R71, R72 R23 R26 R20, R40, R56, R57 R30 562 100 2.87K 2.87K 499 147K 10 10K 1.91K 82.5 0 1K Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% 29 FN6890.0 April 1, 2009 ISL62882, ISL62882B Reference Design Bill of Materials QTY 3 1 1 1 1 1 1 2 2 1 1 REFERENCE R37, R88, R90 R38 R4 R41 R42 R50 R6 R63, R65 R8, R9 R7 U6 VALUE 1 11k DNP 2.61k Thick Film Chip Resistor, 1% GENERIC PANASONIC GENERIC GENERIC GENERIC H2511-02611-1/16W1 ERT-J1VR103J H2511-09311-1/16W1 H2511-08061-1/16W1 H2511-03651-1/16W1 SM0603 SM0603 SM0603 SM0603 SM0805 DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC PART NUMBER H2511-01R00-1/16W1 H2511-01102-1/16W1 PACKAGE SM0603 SM0603 10k NTC Thermistor, 10K NTC 9.31k 8.06k 3.65k TBD 412k Thick Film Chip Resistor, 1% IMVP-6.5 PWM Controller Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% GENERIC INTERSIL H2511-04123-1/16W1 ISL62882HRTZ SM0603 QFN-40 30 FN6890.0 April 1, 2009 ISL62882, ISL62882B Typical Performance 92 90 88 EFFICIENCY (%) 86 82 80 78 76 74 72 70 0 5 10 15 20 25 30 IOUT (A) 35 40 45 50 55 0.96 0.94 0.92 0 5 10 15 20 25 30 35 40 IOUT (A) 45 50 55 60 65 VIN = 19V VIN = 12V VOUT (V) VOUT (V) 84 VIN = 8V 1.10 1.08 1.06 1.04 1.02 1.00 0.98 FIGURE 28. 2-PHASE CCM EFFICIENCY, VID = 1.075V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V FIGURE 29. 2-PHASE CCM LOAD LINE, VID = 1.075V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V 90 85 EFFICIENCY (%) 80 75 VIN = 19V 70 65 60 55 0.1 VIN = 8V 0.885 0.875 VIN = 12V 0.865 0.855 0.845 0.835 0.825 1 IOUT (A) 10 100 0 1 2 3 4 5 6 789 IOUT (A) 10 11 12 13 14 15 FIGURE 30. 1-PHASE DEM EFFICIENCY, VID = 0.875V, DPRSLPVR IS ASSERTED FOR IOUT < 3A VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V. SOLID lINES: ISL62882 EFFICIENCY, DOTTED LINES: WOULD-BE EFFICIENCY IF LGATE1b WAS NOT TURNED OFF IN DPRSLPVR MODE FIGURE 31. 1-PHASE DEM LOAD LINE, VID = 0.875V, DPRSLPVR IS ASSERTED FOR IOUT < 3A VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V. FIGURE 32. SOFT-START, VIN = 19V, IO = 0A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2 FIGURE 33. SHUT DOWN, VIN = 19V, IO = 1A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2 31 FN6890.0 April 1, 2009 ISL62882, ISL62882B Typical Performance (Continued) FIGURE 34. CLK_EN# DELAY, VIN = 19V, IO = 2A, VID = 1.5V, Ch1: PHASE1, Ch2: VO, Ch4: CLK_EN# FIGURE 35. PRE-CHARGED START UP, VIN = 19V, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch4: VR_ON FIGURE 36. STEADY STATE, VIN = 19V, IO = 0A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2 FIGURE 37. STEADY STATE, VIN = 19V, IO = 35A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2 FIGURE 38. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, SV AUBURNDALE 45W CPU TEST CONNDITION: VID = 1.075V, IO = 15A/50A, di/dt = "Fastest" FIGURE 39. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, SV AUBURNDALE 45W CPU TEST CONNDITION: VID = 1.075V, IO = 15A/50A, di/dt = "Fastest" 32 FN6890.0 April 1, 2009 ISL62882, ISL62882B Typical Performance (Continued) FIGURE 40. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, SV AUBURNDALE 45W CPU TEST CONNDITION: VID = 1.075V, IO = 15A/50A, di/dt = "Fastest" FIGURE 41. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, SV AUBURNDALE 45W CPU TEST CONNDITION: VID = 1.075V, IO = 15A/50A, di/dt = "Fastest" FIGURE 42. 1-PHASE DE TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, PSI# = 0, DPRSLPVR = 0, IO = 1A/14A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: COMP, Ch4: LGATE1 FIGURE 43. 1-PHASE DE TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, PSI# = 0, DPRSLPVR = 0, IO = 1A/14A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: COMP, Ch4: LGATE1 FIGURE 44. DEEPER SLEEP MODE ENTRY/EXIT, IO = 1.5A, HFM VID = 1.075V, LFM VID = 0.875V, DEEPER SLEEP VID = 0.875V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, CH4: DPRSLPVR FIGURE 45. VID ON THE FLY, 1.075V/0.875V, 2-PHASE CONFIGURATION, PSI# = 1, DPRSLPVR = 0, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2 33 FN6890.0 April 1, 2009 ISL62882, ISL62882B Typical Performance (Continued) FIGURE 46. PHASE ADDING (PSI# TOGGLE), IO = 1A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: N/A FIGURE 47. PHASE DROPPING (PSI# TOGGLE), IO = 1A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: N/A FIGURE 48. PHASE ADDING (PSI# TOGGLE), IO = 15A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: N/A FIGURE 49. PHASE DROPPING (PSI# TOGGLE), IO = 15A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: N/A Phase Margin Gain FIGURE 50. TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION ENABLED, VIN = 19V, SV CLARKSFIELD CPU TEST CONNDITION: VID = 0.95V, IO = 12A/51A, di/dt="Fastest", Ch1: PHASE1, Ch2: VO, Ch3: N/A, Ch4: LGATE1 FIGURE 51. REFERENCE DESIGN LOOP GAIN T2(s) MESASUREMENT RESULT 34 FN6890.0 April 1, 2009 ISL62882, ISL62882B Typical Performance (Continued) 1000 900 800 IMON-VSSSENSE (mV) 700 Z(f) (m) 600 500 400 300 200 100 0 0 5 10 15 20 25 30 IOUT (A) 35 40 45 50 VIN = 19V SPEC VIN = 12V VIN = 8V 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1k PSI# = 0, DPRSLPVR = 0, 1-Phase DE 10k 100k FREQUENCY (Hz) 1M PSI# = 1, DPRSLPVR = 0, 2-Phase CCM FIGURE 52. IMON, VID = 1.075 FIGURE 53. REFERENCE DESIGN FDIM RESULT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 35 FN6890.0 April 1, 2009 ISL62882, ISL62882B Package Outline Drawing L40.5x5 40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/07 4X 3.60 5.00 A B 36X 0.40 6 6 PIN 1 INDEX AREA PIN #1 INDEX AREA 5.00 (4X) 0.15 TOP VIEW 40X 0.4 0 .1 BOTTOM VIEW 0.20 b 0.10 M 3.50 C AB PACKAGE OUTLINE 0.40 0.750 SEE DETAIL "X" // 0.10 C C BASE PLANE SEATING PLANE 0.08 C SIDE VIEW 0.050 5.00 3.50 (36X 0 ..40) 0.2 REF C 5 (40X 0.20) 0.00 MIN 0.05 MAX (40X 0.60) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 36 FN6890.0 April 1, 2009 ISL62882, ISL62882B Package Outline Drawing L48.6x6 48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07 4X 4.4 6.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0.40 48 1 6 PIN #1 INDEX AREA 6.00 4 .40 0.15 25 (4X) 0.15 24 TOP VIEW 12 13 0.10 M C A B 0.05 M C 48X 0.45 0.10 BOTTOM VIEW 4 48X 0.20 SEE DETAIL "X" 0.10 C BASE PLANE MAX 0.80 ( 5. 75 TYP ) ( 44 X 0 . 40 ) SIDE VIEW C SEATING PLANE 0.08 C ( 4. 40 ) C ( 48X 0 . 20 ) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 48X 0 . 65 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 37 FN6890.0 April 1, 2009 |
Price & Availability of ISL62882
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |